1. Field of the Invention
The present invention relates to switched capacitance circuits and, more particularly to a switched capacitance circuit having an analog/digital converter circuit.
2. Description of the Related Art
As is well known, switched capacitance circuits utilize switches, typically MOS (Metal Oxide Semiconductor) transistors, capacitors and operational amplifiers to perform some analog functions that are normally realized by means of resistances, capacitors and operational amplifiers.
Switched capacitance circuit techniques, developed principally for the purpose of rendering possible the simultaneous integration of analog and digital functions in the same integrated circuit, found their most extensive application in the realization of filters and in the realization of circuits for sampling signals and/or converting data.
In particular, applications relating to signal sampling and data conversion make extensive use of switched capacitance circuits that include a switched capacitance section for sampling (i.e., charging onto the capacitances) an input signal and producing a sampled signal on an output terminal and a second section that includes an operational stage, a comparator stage for example, provided with an input terminal connected to the output terminal of the switched capacitance section for receiving the signal that the section has sampled.
Known applications of this type are the switched capacitance analog/digital converters like those that, for example, function in accordance with SAR (Successive Approximation Register) technique, sometimes also referred to by the expression “charge redistribution converters”.
FIG. 1 illustrates a simplified schematic layout of a portion of a differential analog/digital converter of the SAR type forming part of the prior art.
The shown converter portion includes a switched capacitance section SC capable of receiving a differential input signal VINP, VINM comprising a first VINP and a second VINM signal component. The switched capacitance section SC is also such as to receive a reference signal VREFP, VREFM that is likewise differential.
The switched capacitance section SC includes a first array AR of capacitors Ca, Cb, Cc having a first terminal connected to a first common node NS and a second terminal connected to a respective switch Swa, Swb, Swc.
The switched capacitance section SC further includes a second array AR′ of capacitors Ca′, Cb′, Cc′ having a first terminal connected to a second common node NS′ and a second terminal connected to a respective switch Swa′, Swb′, Swc′.
Furthermore, the converter portion shown in the figure is also provided with an operational stage, in particular a voltage comparator CMP that, by means of the switches Sw1 and Sw1′, can be closed-loop reset.
For the sake of simplicity, the substantially logical part of the analog/digital converter provided for controlling the various switches and functioning in accordance with SAR-type conversion technique has not been shown in FIG. 1.
A delicate phase in the conversion of the analog input signal VINP, VINM into a digital signal is (represented by) the sampling phase of that signal. During this phase the first capacitor array AR has the task of sampling the first component VINP of the differential input signal, while the capacitor array AR′ has the task of sampling the second component VINM of the differential input signal.
In accordance with the layout of FIG. 1, prior designs make extensive use of a technique intended to closed-loop reset the comparator CMP by means of switches Sw1, Sw1′ (during the sampling phase) in order to force the nodes NS, NS′ to a low impedance at a respective voltage value optimal for the operation of the comparator CMP.
For example, a switched capacitance circuit including a closed-loop resettable comparator during the sampling phase of the input signal of a type similar to the one cited above is described in greater detail in the European Patent Application published under the number EP 1039642.
It has been observed that the duration of the transient necessary for charging the capacitances of the switched capacitance section SC becomes particularly critical in applications that call for a high conversion frequency. The duration of this transient is significantly influenced by the impedance seen at the summation nodes NS, NS′ during the sampling phase. In fact, this impedance, together with the values of the capacitances of the switched capacitance section SC, influences the time constant of the charging transient in a decisive manner. When the duration of this transient has to be reduced, it is typically not possible to act on the capacitances of the switched capacitance section because, as is well known to persons skilled in the art, the values of these capacitances are predetermined and unchangeable, since they are essentially imposed by the resolution of the converter.
With a view to increasing the speed at which the input voltage can be charged onto the capacitors of a switched capacitance circuit that includes a closed loop resettable comparator of the type described above, a possible solution would be constituted by redesigning the comparator CMP in such a manner as to increase the current that the comparator is capable of providing to the summation nodes NS, NS′ (for charging the capacitors of the switched capacitance section SC).
It has been observed that this solution is associated with some drawbacks. In particular, the power consumption of the comparator CMP becomes significantly greater when this current is increased. This is due to the fact that all the generators within the comparator have to provide a greater current for the purpose of continuing to assure the biasing and frequency response performances necessary for settling the comparator.
Furthermore, maintenance of the biasing performances (which include maintenance of the common mode voltage of the comparator at the value that makes it possible to optimize the comparator performances) calls for an increase of the aspect ratio W/L of the MOS transistors within the comparator CMP and this determines a considerable increase of the area occupied by the comparator.
Though here described with particular reference to an analog/digital converter, these problems are nevertheless quite generally associated with circuits that provide switched capacitances upstream of a converter stage or, more generally, an operational stage.